1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and more particularly to a method of manufacturing a semiconductor device applied, for example, to manufacture of semiconductor integrated circuits having memory devices which are highly refined and integrated, or semiconductor integrated circuits in which memory devices and logic devices are disposed together.
2. Description of the Related Art
In recent years, as semiconductor integrated circuits developed greatly for high integration degree and high performance, DRAMs have been known for instance. Since a memory cell portion containing one bit of information can be formed as an assembly of a less number of devices, namely, one transistor and one capacitor in DRAM, it is suitable to increase the capacity and has played a leading role in highly advanced refining processes.
Memory capacity of DRAM has been increased by as much as four times in about three years. Further, the chip area has been increased by 1.5 times on every generation. However, the memory cell area has been reduced to 1/3. Meanwhile, for enabling reading by a sensing amplifier and in order to prevent occurrence of .alpha.-ray induced soft errors, an identical storage capacity is demanded for a charge retaining capacitor even if the memory cell area is reduced as described above, for example, it is necessary to ensure the value of from 20 to 30 fF. Then, it has become necessary to increase the capacitor area or use a film of high specific dielectric constant as a dielectric film of the capacitor.
Recently, tantalum oxide has been expected as a film of high specific dielectric constant. The film has an extremely higher specific dielectric constant of 23 compared with the specific dielectric constant of 7.5 of a silicon nitride film used mainly as the dielectric film for the capacitor so far.
By the way, in the manufacture of an usual DRAM, as shown in FIG. 4, a substrate body 50 having an interlayer insulation film 52 formed on a semiconductor substrate 51 having a cell region (1) for forming a memory cell portion and a circuit region (2) for forming a peripheral circuit portion is used. When the memory portion and the peripheral circuit portion are formed to the substrate body 50, a step of forming a capacitor 55 comprising a lower electrode 55a, a dielectric film 55b and an upper electrode 55c is carried out and then a step of forming the peripheral circuit to the circuit region (2) is conducted. This is because the step of forming the capacitor 55 includes a heat treatment step at a higher temperature than that in the step of forming the peripheral circuit and, accordingly, if the peripheral circuit is formed previously, a disadvantage is caused to the peripheral circuit portion by the heat treatment step in the subsequent step of forming the capacitor 55.
For instance, in the step of forming the peripheral circuit, a connection hole 57 for connecting a diffusion layer 56 formed on a semiconductor substrate 51 and a wiring formed on the substrate body 50 is formed through interlayer insulation films 52, 53 and 54 on the semiconductor substrate 51 of the circuit region (2) till the hole reaches the diffusion layer 56. Subsequently, a step of burying tungsten by way of a barrier metal layer in the connection hole 57 thereby forming a tungsten plug for joining with the diffusion layer 56 is conducted.
Accordingly, when the tungsten plug is formed by conducting the step of forming the peripheral circuit before the step of forming the capacitor 55, a heat treatment for activating impurities in a polysilicone film forming the lower electrode 55a in the step of forming the capacitor 55 results in a phenomenon that the barrier metal layer of the tungsten plug penetrates the diffusion layer 56 to reach the semiconductor substrate 51. As a result, junction leak is caused at a joined portion between the tungsten plug and the diffusion layer 56. Therefore, the step of forming the peripheral circuit in the circuit region (2) is conducted after the step of forming the capacitor 55 in the cell region (1). The step of forming a bit line 58 on the substrate body 50 in the cell region (1) is connected before the step of forming the peripheral circuit.
Further, when the connection hole 57 is formed to the interlayer insulation films 52, 53 and 54 of the circuit region (2) in the step of forming the tungsten plug in the step of forming the peripheral circuit, a photolithographic step and a drying etching step are used. However, misalignment may sometimes be caused upon conducting mask alignment relative to a device isolation region 59 comprising a silicone oxide film in the photolithographic step, for manufacturing a highly integrated DRAM as described above, to form the connection hole 57 in a state overlapped partially with the end of the device isolation region 59. In this case, the device isolation region 59 is engraved to expose the underlying semiconductor substrate 51 and, if it is left as it is, leak current is caused when a conductive material is buried into the connection hole 57 in the subsequent step.
In view of the above, in recent years, as shown in FIG. 5, impurity ions are implanted through the connection hole 57 to the diffusion layer 56 exposed at the bottom of the connection hole 57 (contact compensating ion implantation), and then the implanted impurities are activated in the semiconductor substrate 51 by a heat treatment at a temperature higher than that for the formation of the polysilicon film, for example, at about 800.degree. C., to form a compensating diffusion layer 60, thereby preventing occurrence of the leak current.
By the way, in the method of manufacturing the semiconductor device of the prior art, if the step of forming the compensating diffusion layer is introduced to the step of forming the peripheral circuit as described above, an activating heat treatment at a higher temperature is conducted in the step of forming the compensating diffusion layer after the step of forming the capacitor. Therefore, if a tantalum oxide film is used as the dielectric film in the step of forming the capacitor, tantalum oxide and the lower electrode of the capacitor are reacted by the activating heat treatment applied subsequently to result in a disadvantage that the lower electrode is oxidized to lower the effective capacity. For example, when polysilicon is used for the lower electrode of the capacitor, the polysilicon forms silicon oxide having a specific dielectric constant as low as 4 to lower the capacity.
For preventing oxidation of the polysilicon as the lower electrode upon activating heat treatment described above, it may be considered to interpose a silicon nitride film 61 between the lower electrode 55a and the dielectric film 55b comprising tantalum oxide for preventing oxidation of the polysilicon as shown in FIG. 5. However, since the specific dielectric constant of the silicon nitride film 61 is 7.5, lowering of the capacity is inevitable also in this case.
Further, it has been considered to use tungsten which can be formed at a lower temperature instead of polysilicon undergoing a heat treatment at high temperature as the material for forming the lower electrode of the capacitor. However, tungsten is also oxidized through the activating heat treatment at a high temperature in the step of forming the compensating diffusion layer described above to result in lowering of the capacity of the capacitor. In addition, since the oxides of tungsten is sublimating, tungsten is swollen to no more serve as the lower electrode.
From the foregoings, it has been demanded for the development of a technique for forming DRAM not resulting in the lowering of the capacity of the capacitor even when a film of a highly dielectric constant such as a tantalum oxide film is used as the dielectric film for the capacitor and even if a step of forming the compensating diffusion layer is conducted in the step of forming the peripheral circuit.
Further, the reading performance of DRAM is improved more as the resistance of a bit line as a path for electric charges is lower, but tungsten polycide (WSi).sub.x /poly-Si) which is not low resistance material is used as the material for forming the bit line since it is resistant to heat in the step of forming the compensating diffusion layer in the step of forming the peripheral circuit at present. As described previously, when tungsten having resistance lower than that of tungsten polyside is intended to be used as the material for forming the bit line, since the bit line is formed also prior to the step of forming the peripheral circuit as described above, it reacts with oxygen atoms in silicon oxide of the interlayer insulation film in contact with tungsten and gases evolved from the interlayer insulation films, during activating heat treatment in the step of forming the compensating diffusion layer, to also result in a problem of causing failure such as disconnection of the bit line. Accordingly, it has also been highly demanded for the development of a technique capable of lowering the resistance of the bit line without causing failure to the bit line.